2026-01-052026-01-05https://repositorio.uandes.cl/handle/uandes/62450<p>Extended reality (XR) applications are machine learning (ML)-intensive, featuring deep neural networks (DNNs) with millions of weights, tightly latency-bound (10-20 ms end-to-end), and power-constrained (low tens of mW average power). While ML performance and efficiency can be achieved by introducing neural engines within low-power systems-on-chip (SoCs), system-level power for nontrivial DNNs depends strongly on the energy of non-volatile memory (NVM) access for network weights. This work introduces Siracusa, a near-sensor heterogeneous SoC for next-generation XR devices manufactured in 16 nm CMOS. Siracusa couples an octa-core cluster of RISC-V digital signal processing (DSP) cores with a novel tightly coupled 'At-Memory' integration between a state-of-the-art digital neural engine called N-EUREKA and an on-chip NVM based on magnetoresistive random access memory (MRAM), achieving 1.7× higher throughput and 3× better energy efficiency than XR SoCs using NVM as background memory. The fabricated SoC prototype achieves an area efficiency of 65.2 GOp/s/mm² and a peak energy efficiency of 8.84 TOp/J for DNN inference while supporting complex, heterogeneous application workloads, which combine ML with conventional signal processing and control.</p>info:eu-repo/semantics/restrictedAccessArtificial intelligence (AI)RISC-Vaugmented reality (AR)deep neural network (DNN)extended reality (XR)heterogeneous architecturemagnetoresistive random access memory (MRAM)non-volatile memory (NVM)system-on-chip (SoC)SDG 7 - Affordable and Clean EnergyArticle