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dc.contributor.advisor33
dc.contributor.authorPrasad, Arpan Suravi
dc.contributor.authorScherer, Moritz
dc.contributor.authorConti, Francesco
dc.contributor.authorRossi, Davide
dc.contributor.authorDi Mauro, Alfio
dc.contributor.authorEggimann, Manuel
dc.contributor.authorGomez, Jorge Tomas
dc.contributor.authorLi, Ziyun
dc.contributor.authorSarwar, Syed Shakib
dc.contributor.authorWang, Zhao
dc.contributor.authorDe Salvo, Barbara
dc.contributor.authorBenini, Luca
dc.coverageDOI: 10.1109/JSSC.2024.3385987
dc.date2024
dc.date.accessioned05-01-2026 18:06
dc.date.available05-01-2026 18:06
dc.date.issued33
dc.description.abstractExtended reality (XR) applications are machine learning (ML)-intensive, featuring deep neural networks (DNNs) with millions of weights, tightly latency-bound (10-20 ms end-to-end), and power-constrained (low tens of mW average power). While ML performance and efficiency can be achieved by introducing neural engines within low-power systems-on-chip (SoCs), system-level power for nontrivial DNNs depends strongly on the energy of non-volatile memory (NVM) access for network weights. This work introduces Siracusa, a near-sensor heterogeneous SoC for next-generation XR devices manufactured in 16 nm CMOS. Siracusa couples an octa-core cluster of RISC-V digital signal processing (DSP) cores with a novel tightly coupled 'At-Memory' integration between a state-of-the-art digital neural engine called N-EUREKA and an on-chip NVM based on magnetoresistive random access memory (MRAM), achieving 1.7× higher throughput and 3× better energy efficiency than XR SoCs using NVM as background memory. The fabricated SoC prototype achieves an area efficiency of 65.2 GOp/s/mm<sup>2</sup> and a peak energy efficiency of 8.84 TOp/J for DNN inference while supporting complex, heterogeneous application workloads, which combine ML with conventional signal processing and control.
dc.identifierhttps://investigadores.uandes.cl/en/publications/51b2099f-196a-409e-a9ff-1e515db57a91
dc.identifier.citation33
dc.identifier.uri33
dc.languageeng
dc.language.iso33
dc.publisher33
dc.relation33
dc.rightsinfo:eu-repo/semantics/restrictedAccess
dc.sourcevol.59 (2024) date: 2024-07-01 nr.7 p.2055-2069
dc.subjectArtificial intelligence (AI)
dc.subjectRISC-V
dc.subjectaugmented reality (AR)
dc.subjectdeep neural network (DNN)
dc.subjectextended reality (XR)
dc.subjectheterogeneous architecture
dc.subjectmagnetoresistive random access memory (MRAM)
dc.subjectnon-volatile memory (NVM)
dc.subjectsystem-on-chip (SoC)
dc.subjectSDG 7 - Affordable and Clean Energy
dc.title33
dc.titleSiracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engineeng
dc.title33spa
dc.title33und
dc.type33
dc.typeArticleeng
dc.typeArtículospa
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